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mp 8003a ieee 802.3 af/ at , poe , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 1 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. description the MP8003A is an ieee , 802.3 af/ at , power over ethernet ( poe ) compliant , powered d evice (pd) , interface controller . the MP8003A has all the function s of ieee 802.3 af/ at, including detection, 1 - event and 2 - event classification, input current con trol , and a 100v hot - swap mosfet . the MP8003A sets the inrush current limit at about 120ma d uring start - up and switch es to 8 4 0ma when the output pass mosfet is turned on completely . a pg signal set to high indicate s when the outpu t is fully charged and pulls low when the output drops under the overload condition. the MP8003A also provide s a t2p signal when it is connected to type - 2 power sourcing equipment (pse). an auxiliary power input detector ( aux ) provides a smooth power switc h from pse to an auxiliary wall adapter . the MP8003A also features built - in t hermal protection and a wide - input uv lo hysteresis . t he MP8003A is available in a qfn - 10 ( 3 mmx 3 mm ) package. features ? compatible with 802.3af/at s pecifications ? 100v , 0.48 integrated pass switch ? 1 2 0ma inrush current limit ? 8 4 0ma operation current l imit ? 2 - event classification ? auxiliary adapter o - ring power supply ? self - driving power good i nductor ? open - drain type - 2 pse i ndicator ? over - temperature p ro tection (otp) ? available in qfn - 10 ( 3 mmx3 mm) package applications ? ieee 802.3 af/ at - compliant devices ? security camera s ? voip phones ? wlan access points ? iot devices all mps parts are lead - free, halogen - free, and adhere to the rohs directive. for mp s green status, please visit mps website under quality assurance. mps and the future of analog ic technology are registered trademarks of monolithic power systems, inc. typical application c 1 d e t r t n v d d c l a s s v s s r 1 r 2 t 2 p f t y d 1 p g d c / d c c o n v e r t e r c 2 m p 8 0 0 3 a 4 8 v f r o m p s e a u x v d d v s s a d a p t o r e n d 2 d 3 r 3 r 4
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 2 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. ordering information p art number * package top marking MP8003Agq qfn - 10 (3 mm x 3 mm ) see below * for tape & reel, add suffix C z (e.g. MP8003Agq C z) top marking a nu : product code of MP8003Agq y: year code lll: lot number package reference top view qfn - 10 (3mmx3mm) 1 v s s 1 0 r t n 2 f t y 9 n c 3 c l a s s 8 p g 4 t 2 p 7 v d d 5 a u x 6 d e t
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 3 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. absolute maximum rat ings (1) vdd, rtn, det, t2p, aux to vss ................... ................................ .................. - 0.3v to +100v class , fty to vss ................... - 0.3v to +6.5v pg to rtn ................................ .. - 0.3 v to + 6.5 v aux to vdd ............................ - 6.5 v to + 0.3 v ( 2 ) t2p sinking current ................................ ... 10 ma aux sinking current .............................. - 5 ma ( 2 ) pg sinking current ................................ . 1ma ( 3 ) continuous power dissipation (t a = + 25 c) ( 4 ) ................................ ................................ .. 2.5w junction temperat ure ............................... 150 c lead temperature ................................ .... 260 c storage temperature ................ - 65c to +150c recommended operating conditions ( 5 ) supply voltage ( v dd ) .......................... 0v to 57v t2p sinking current ................................ ..... 5 ma maximum aux sinking current .............. - 3 ma ( 2 ) maximum pg sinking current .............. 0.6 ma (3) thermal resistance ( 6 ) ja jc qfn - 10 (3mmx3mm) ............ 50 ....... 12 ... c/w notes : 1) exceeding these ratings may damage the device. 2) when vdd to the adapter ground voltage is high, the aux - vdd voltage may exceed - 6 . 5v if the divider resistor is not a ppropriate . in this condition , vdd clamp s the - 6 .5v voltage on aux, but the current should be limit ed by the external resistor. 3) if pg is pulled up higher than 6.5v externally, the pull - up current should be limited. refer to the power good (pg) indicator signal section on page 14 for more detail s . 4) the ma ximum allowable power dissipation is a function of the maximum junction temperature t j (max), t he junction - to - ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max) - t a )/ ja . exceeding the maximum allowable power dissipation pr oduces an excessive die temperature, causing the regulator to go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 5) the device is not guaran teed to function outside of its operating conditions. 6) measured on jesd51 - 7, 4 - layer pcb. operating junct ion temp (t j ) .... - 4 0 c to +125 c
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 4 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. electrical character istics v dd = 48v, all voltages are with respect to v ss , r det = 24.9k, r class = 28.7 , t j = - 40c to + 125c, typical values are tested at t j = 25 c, unless otherwise noted. parameter symbol condition min typ max units detection detection on v det - on v dd rising 1.9 v detection off v det - off v dd rising 1 1 v det leakage c urrent i det - lk v det = v dd = 57v, measure i det 0.1 5 a bias current v dd = 10.1v, float det, not in m ark event , m easure i supply 12 a detection current i det v dd = 2 .5v, me asure i supply 96 99 102 a v dd = 10.1v, measure i supply 395 410 425 a classification classification stability time 90 s v class output voltage v class 13v < v dd < 21v 1ma < i class < 4 2 ma 1.1 1.16 1.2 1 v classificatio n current i class 13 v vdd 21v, guaranteed by v class r class = 578 , 13v v dd 21v 1.8 2 2.4 ma r class = 110 , 13v v dd 21v 9.9 10.55 11. 3 r class = 62 , 13v v dd 2 1v 17.7 18.7 19. 8 r class = 41.2 , 13v v dd 21v 26.6 28.15 29.7 r class = 28.7 , 13v v dd 21v 38.2 40.4 42.6 classification lower threshold v cl - on re gulator turns on, v dd rising 11. 8 12.5 13 v classification upper threshold v cl - off regulator turns off, v dd rising 21 22 23 v classification hysteresis v cl - hys low - side hysteresis 0.8 v high - side hysteresis 0.5 mark event reset threshold v mark - l 4.5 5 5.5 v max mark event voltage v mark - h 11 11. 5 12 v mark event current i mark 0.5 1.5 2 ma mark event resistance r mark 2 - point measure at 7v and 10v 12 k ic supply current during classification i in - class v dd = 17.5v, class floating 220 300 a class leakage current i leakage v class = 0 v, v dd = 57v 1 a uvlo vdd turn on threshold v dd - vss - r v dd r ising 3 5 37.5 4 0 v vdd turn off threshold v dd - vss - f v dd f alling 29 3 1 3 3 v vdd uvlo hysteresis v dd - vss - hys 4.9 v ic supply c urrent during operation i in 450 a
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 5 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. electrical character istics (continued) vdd = 48v, all voltages are with respect to vss , r det = 24.9k, r class = 28.7 , t j = - 40c to +125c, typical values are tested at t j = 25 c, unl ess otherwise noted. parameter symbol condition min typ max units pass device and current limit on r esistance r on - rtn i rtn = 600ma 0.4 8 leakage c urrent i rtn - lk v dd = v rtn = 57v 1 15 a current l imit i limit v rtn = 1v 720 8 4 0 9 2 0 ma inru sh l imit i inrush v rtn = 2v 1 2 0 ma inrush current termination v rtn f alling 1.2 v inrush to operation mode delay t delay 80 100 ms current foldback t hreshold v rtn r ising 10 v foldback deglitch time v rtn rising to inrush curren t foldback 1 ms t2p t2p output low voltage i t2p = 2ma, respect to vss 0.1 0.3 v t2p high leakage current v t2p = 48v 1 a aux aux high threshold voltage ( 7 ) respect to vdd - 2.3 v aux low threshold voltage ( 7 ) respect to vdd - 0. 6 v aux leakage c urrent v dd - v aux = 6v 2 a pg pg output high voltage pg floating 5.5 v pg source current pg = h igh , force pg = 4v 7 a pg pull - down resistance pg is logic low, pull pg up to 1 v 1000 k thermal shutdown thermal s hutdown t emperatu re ( 8 ) t sd 1 5 0 c thermal s hutdown hysteresi s ( 8 ) t hys 20 c notes : 7) vdd - aux > 2.3v, ic enable adapter input . if vdd - aux < 0.6v, ic enable s the pse input. refer to the wall power adapter detection and operation section on page 12 for the aux setting. 8) guaranteed by engineering sample characterization .
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 6 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical performance characteristics v in = ( v dd - v ss ) = 48v, r det = 2 4.9k , r class = 28.7 , t a = 25c, unless otherwise noted.
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 7 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical performance characteristics (continued) v in = ( v dd - v ss ) = 48v, r det = 24.9k , r class = 28.7 , t a = 25c, unless otherwise noted.
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 8 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical performance characteristics (continued) v in = ( v dd - v ss ) = 48v, r det = 24.9k, r class = 28.7, t a = 25c, unless otherwise noted.
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 9 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. pin functions pin# name description 1 vss negati ve power supply terminal from the po e input power rail. 2 fty factory use only . fty must be connected to vss during application. 3 class pow er class . connect resistor from class to vss to program the classification current. 4 t2p type - 2 pse indictor , open - drain output. t2p is pulled low to vss to indicate the presence of a type - 2 pse or if aux is enabled. 5 aux auxiliary power i nput detector . use aux for adapter auxiliary power application s . drive vdd - aux higher than 2.3 v to disable the hot - swap mosfet and class function and force t2p and pg active. 6 det detection . connect a 2 4.9 k resistor between vdd and det for po e detection. 7 vdd positive power supply terminal from the po e input power rail. 8 pg pd supply power good indicator. the pg signal can be used to enable the downstream dc / dc converter. pg is pulled up by an internal current source in output - high condition and can be floated during application. 9 n c no connection. nc is not connected internally, but can be connected to vss and the exposed thermal pad during layout. 10 rtn drain of pd hot - swap mosfet . connect the next stage dc/dc converters power return terminal to rtn .
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 10 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. block diagram f igure 1 : functional block diagram d e t e c t i o n 2 . 7 v - 1 0 . 1 v c l a s s i f i c a t i o n 1 4 . 5 v - 2 0 . 5 v m a r k e v e n t 6 . 9 v - 1 0 . 1 v v d d d e t c l a s s i n r u s h a n d c u r r e n t l i m i t c o n t r o l l o g i c a n d g a t e d r i v e r v s s r t n t 2 p s t a r t - u p d e l a y c o n t r o l a u x p g c u r r e n t / v o l t a g e s e n s e 2 4 . 9 k r c l a s s c l o a d 5 . 5 v c u r r e n t
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller mp 8003a rev. 1.0 www.monolithicpower.com 11 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mp s. all rights reserved. operation compared with ieee 802.3af, the iee e 802.3at standard establishes a higher power allocation for power over ethernet (poe) while maintaining backwards compatibility with existing ie ee 802.3af systems. power sourcing equipment ( pse) and powered devices (pd) are distinguished as type - 1 ( complying with ieee 802.3af power levels ) or type - 2 ( complying with the ieee 802.3at power levels ) . the ieee 802.3 af/ at standard estab lishes a method of communication between pd and pse with detection, classification , and event mark. the mp8003 a is an ieee 802.3 af/ at poe pd interface . the MP8003A operates as a safety device that supplies voltage only when the power sourcing equipment rec ognizes a unique, tightly specified resistance at the end of an unknown length of ethernet cable. if the pse sees the correct load, then it increase s the applied voltage further to enter the classification operation range and switch o n the nominal 48v power to the load. figure 2 shows the typical pd interface power operation sequence . figure 2 : pd interface operation description detection r det connected between det and vdd is presented as a load to t he pse in detection mode . when the pse applies two safe voltages between 2.7v to 10.1v while measuring the change in current drawn to determine the load resistance. a 24.9k? (1%) resistor between vdd and det is recommended to present one correct signature . the valid signature resistance seen from the power interface (pi) is between 23.7k? and 26.3k?. the detection resistance seen from the pi is the result of the input bridge resistanc e in series with the vdd load . the input bridge resistance is cancell ed partially by the effective leakage resistance during detection. classification the classification mode can specify the expected load range of the device un der power to the pse so that the pse can distribute power intelligently to as many loads as it can within its maximum current capability. the classification mode is active between 14.5v and 20.5v. the MP8003A present s a current in classification mode (see table 1). 2 . 7 v 6 . 9 v 1 4 . 5 v 2 0 . 5 v 3 7 v 4 2 . 5 v 5 7 v 1 0 . 1 v v 1 v 2 s i g n a t u r e r a n g e m a r k r a n g e c l a s s i f i c a t i o n r a n g e 6 . 9 - 1 0 . 1 v 2 . 7 - 1 0 . 1 v 1 4 . 5 - 2 0 . 5 v 3 7 - 5 7 v ( a f ) 4 2 . 5 - 5 7 v ( a t ) i e e e 8 0 2 . 3 a f s t a r t - u p i e e e 8 0 2 . 3 a t s t a r t - u p c l a s s e v e n t 1 c l a s s e v e n t 2 o n r a n g e r e s e t s i g n a t u r e c l a s s i f i c a t i o n i n t e r m e d i a t e i d l e o n t u r n o n v o l t a g e t i m e m a r k e v e n t
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 12 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. table 1 : class resistor selection class max input power to pd (w) classification current (ma) r class () 0 12.95 2 578 1 3.84 10.55 110 2 6.49 18.7 62 3 12.95 28.15 41.2 4 25.5 40 .4 28.7 2 - event classification the MP8003A can be used as a type - 1 pd class 0 - 3 (as shown in table 1 ). it also distinguishes class 4 with 2 - event classification. in 2 - event classification, the type - 2 pse read s th e powe r classification twice. figure 2 shows an example of a 2 - event classification. the first classification event occurs when the pse presents a voltage between 14.5v to 20.5v to the MP8003A , and the MP8003A presents a class - 4 load current. the pse then drops the input voltage into the mark voltage range of 6.9v to 10.1v signaling the first mark event. the MP8003A presents a load current between 0.5ma to 2ma in the mark event voltage range . the pse repeats this sequence, signaling the second classification and second mark event. the pse then applies power to the MP8003A , which charges up the downstream dc / dc input capacitor ( c 2 ) with a controlled inrush current. when c 2 is fully charged, t2p presents an active low signal with respect to vs s after t delay . the t2p output becomes inactive when the MP8003A input voltage ( vdd ) falls below uvlo (see figure 3 ) . under - voltage lockout (uvlo) and current limit when the pd voltage is powered by pse , and vdd is higher than the turn - on threshold, the ho t - swap switch start s pass ing a limited current ( i inrush ) to charge the downstream dc / dc converters input capacitor. the start - up charging current is around 120ma . i f rtn drops below 1.2v, the hot - swap current limit switches to 8 4 0ma . a fter the t delay from uvlo begins , the MP8003A assert s the pg signal and switches from start - up mode to normal operation mode. the pg signal can enable the downstream dc / dc converter directly. if vdd - vss drops below the input falling uvlo threshold , the hot - swap mosfet is disabled. if the output current overload s on the internal pass mosfet, the current limit work s , and v rtn - vss rises . if v rtn rises above 10v for longer than 1ms or rises above 20v, the current limit reverts to the inrush value and pulls down pg simultaneously . figure 3 shows the current limit, pg , and t2p work logic during start - up from the pse power supply. figure 3 : start - u p sequence wall power adapter detection and operation for applications where an auxiliary power source such as a wall adapter is used to power the device, the MP8003A features wall power adapter detection (see figure 4 ) . onc e t he input voltage ( vdd - vss ) exceeds about 11.5v , the MP8003A enable s wall adapter detection. the wall power adapter detection resistor divider is connected from vdd to the n egative terminal of an adapter . d adp3 in figure 4 is added for more accurate hys teresis . there is a - 2 .3v turn - on voltage from aux to vdd for adapter detection. p s e p o w e r o n v d d > u v l o _ r ? 1 2 0 m a i n r u s h v r t n - v s s < 1 . 2 v ? c u r r e n t l i m i t c h a n g e t o 8 4 0 m a 1 0 0 m s t i m e r t i m e r - o u t ? y e s y e s y e s n o n o n o p g r i s e s t o h i g h t 2 p a c t s b a s e d o n p s e t y p e b o t h a r e o k v r t n > 1 0 v f o r 1 m s o r v r t n > 2 0 v ? y e s p g d r o p s v d d < u v l o _ f ? y e s t 2 p r e s e t s n o p s e p o w e r o f f
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller mp 8003a rev. 1.0 www.monolithicpower.com 13 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mp s. all rights reserved. the adapter is detected when equation (1) is met : (1) where v adp is the adapter voltage, v dadp3 is the zener voltage , and r a dpup and r adpdown are the aux divider resist o r s from the adapter power. if applied adapter voltage is much higher than the design adap t er voltage, the vdd - v aux voltage is high . if the applied adapter voltage is high er than 6.5v, the MP8003A inner circu i t clamp s the vdd - v aux voltage at 6.5v . a current then flow s out through aux . the current should be limited below 3ma by an external resistor (r adpup / r adpdown or r t from the resistor divider to aux) . to make the MP8003A work stably with adapter power, one s chottky diode ( d a dp 1 , d 2 in the schematic on page 1 ) is required between the negative terminal of the adapter and vss. d a dp 2 (d 3 in the schematic on page 1) is used to block reverse current betwe en the adapter and pse power source. when a wall adapter is detected, the internal mosfet between rtn and vss turns off, the classification current is disabled , and t2p becomes active . t he pg sign al is active when the adapter power is detected so that it can enable the downstream dc / dc converter , even if the input hot - swap mosfet is disabled. figure 4 : adapter power detection power good indi c a tor (pg) the pg signal is driven by the internal cur rent source. after t delay from uvlo starts, and rtn drops to 1.2v, or a wall power adapter is detected, the pg signal is pulled high to indicate the output power condition and enable the downstream dc / dc converter . figure 3 shows the pg logic when powered from pse. pg is high if the adapter is detected . thermal shutdown the MP8003A has a temperature protecti on circuit . when the junction temperature exceeds 150c, the ic shuts down. the ic recovers with limited inrush current if t he junction temperature drops below 130c. adpup dd aux adp dadp3 adpup adpdown r v v (v v ) 2.3v rr ? ? ? ? ? ? v d d v s s r t n a d a p t o r + - a u x s h u t d o w n h o t - s w a p s h u t d o w n c l a s s i f i c a t i o n p u l l u p p g t o d c d c 2 . 3 v f r o m p s e m p 8 0 0 3 a r a d p u p r a d p d o w n d a d p 1 d a d p 2 d a d p 3
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 14 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. application informat ion detection resistor in detection mode , a resistor connected between det and vdd is required as a load to the pse . the resistance is calculated as ? v/ ? i with an acceptable rang e of 23.7k to 26. 3k. use a typical value of 24.9 k as a detection resistor. classification resistor to distribute power to as many loads as possible from pse, a resistor between class and vss is used to classify the pd power leve l , which draws a fixed c urrent set by the classification resistor. the supplied power set by the classificati on resistor is shown in table 1. the typical voltage on class is 1. 16v in the classification range and produces about 47mw of power loss on the class r esistor , even in c lass - 4 condition . protection tvs to limit the input transient voltage within the absolute maximum ratings, a tvs across the rectified voltage ( vdd - vss ) must be used. a smaj58a tvs or equivalent is recommended for general indoor applic ations. outdoor transient levels or special applications require additional protection. pd input capacitor a 0.05f to 0.12f input bypass capa citor from vdd to vss is needed for ieee 802.3at standard specification s . typically , a 0.1f, 100v , ceramic capacitor is sufficient . wall power adapter detection c ircuit when an auxiliary power source , such as a wall power adapter , is used to power the device , the divider resistors , r adpup , r adpdown , and d adp3 should be chosen to satisfy equation (1) f or correct wall power adapter detection (see figure 5) . r adpup with a typical 3k value is recommended to balance power loss and d adp1 and d adp2 leakage current discharge. figure 5 : wall adapter detection circuit one small schott ky diode with a 100v voltage rating , such as bat46w , is suggested for d adp1 , typically . the voltage rating of d adp2 must also be 100v or higher , while the current rating must be higher than the load current. a low voltage drop schottky diode , such as ss1h1 0 , is recommended to reduce conduction power loss . the MP8003A enable s wall adapter detection when vdd is 11.5v. if one adapter power with a lower voltage rating ( such as 10v ) is used to power the converter, one external pg pull - up circuit is necessary to enable the downstream dc / dc converter . power good (pg) indicator signal the MP8003A integrates one pg indicator . since pg is pulled high through an internal pull - up current source when the logic is high, it can be used to enable the downstream dc / dc converter without a n external pull - up circuit. pg disable s the internal pull - up current and is pull ed low through a 1m internal re sistor when pg is in a logic - low state. if there is a low resistance pull ing down on en of the downstream converter, some external pg pull - up current is needed . the MP8003A can provide 7 a of pull - up current . if pg is pulled up higher than the 5.5v power source, the pg sink current should be limited to protect the internal clamp zener diode. normally , an input current 0.6ma or lower on pg is suggested. if one adapter power less than 11.5v is connected to supply the converter, the pg function cannot work with s uch a low input . the external pg pull - up circuit is recommended (see figure 5) . typically, q pg requires a v ce voltage higher than 100v , such as bss63lt1 . choose r pg2 = 7.5k and r pg3 = 100k for a 12v adapter with some adapter regulation margin , and choose r pg1 = 100k to limit the pg sink current. v d d a u x v s s r t n v a d p a d a p t o r g n d r a d p u p r a d p d o w n d a d p 1 d a d p 2 d a d p 3 p g q p g r p g 1 r p g 2 r p g 3
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller mp 8003a rev. 1.0 www.monolithicpower.com 15 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mp s. all rights reserved. t2p indicator connection t2p is an active - low, open - drain output which indicates the presence of a type - 2 pse o r adapter power . an optocoupler is used as the interface from t2p to the circuitry on the output of the converter , typically (see figure 6 ) . a high - gain optocoupler and a high - impedance receiver ( i.e.: cmos) are recommended. figure 6 : t2p inductor circuit considering the t2p sinking current ( typically 2ma), the t2p output low voltage 0.1v , and the diode forward voltage drop, choose r t2p to be 23.7k ?. suppose v out of the dc / dc c onverter is 12 v . to match the typical 48v input , choose r t2p - o = 20k? based on the crt , though it may vary with temperature, led bias current , and aging. if using a n led from vdd to t2p to indicate t2p activity, the r t2p s resistance can be higher to match the led s max current and reduce p ower loss . pcb layout guidelines efficient layout of the poe front end should guarantee solid performance, low power loss , and no emi/esd problem s . the spacing between vdd (48v) and vs s must comply wit h safety standards such as iec60950 . for best results, refer to figure 7 and follow the guidelines below. 1. ensure that all component place ment follow s the power flow f rom rj - 45 to the ethernet transformer to the diode bridges to tvs to the 0.1 f capacitor to the dc / dc converter input bulk capacitor. 2. make all leads as short as possible with wide power traces . 3. place the MP8003A local ground planes referenced to v ss . 4. place the next - st age dc / dc converter ground planes referenced to rtn . 5. connect the exposed pad to vss , since it is used to heat sink the part to the circuit board traces . 6. place large copper traces and vias on the exposed pad and v ss trace for thermal dissipation . figure 7 shows the recommende d component place ment for the MP8003A based on the schematic on page 1 . figure 7 : recommend ed layout design example table 2 is a design example following the applicati on guidelines for the following specifications . t a ble 2 : design example v dd - v ss 48v r det 24.9k? r class 28.7? v adapter 12 v the typical application circuit in figure 8 shows the detailed application schematic, and is the basis for the typical performance characteristics section . typically, the devi ce is powered by pse ( v dd - v s s = 48v) . when an adapter voltage a b ove 9.6v is present, the internal mosfet between rtn and vss turns off . instead , the device is pow er ed by the adapter regardless of what the pse voltage is . for more detailed d evice applications, please refer to the related evaluation board datasheet . v d d t 2 p i t 2 p r t 2 p v o u t o f d c / d c i t 2 p - o u t t y p e - 2 i n d u c t o r l o w a c t i v e r t 2 p - o 1 v s s 1 0 r t n 2 f t y 9 n c 3 8 p g 4 t 2 p 7 v d d 5 a u x 6 d e t r 3 r 4 c 1 d 1 r 1 r 2 d 3 d 2 r t n a p d g n d v d d / v a p d v s s m p 8 0 0 3 a c 2 c l a s s
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller MP8003A rev. 1 .0 www.monolithicpower.com 16 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical application circuits figure 8 : typical application circuit, vdd - vss = 48v , v adapter = 12 v f igure 9: typical application circuit, vdd - vss = 48v , no a dapter input c 1 0 . 1 f 1 0 0 v d e t r t n v d d c l a s s v s s r 1 2 4 . 9 k r 2 2 8 . 7 t 2 p f t y d 1 s m a j 5 8 a p g d c d c c o n v e r t e r m p 3 9 1 0 m p 3 9 0 8 m p 6 0 0 2 m p 6 0 0 4 m p 6 0 0 1 c 2 4 7 f m p 8 0 0 3 a 4 8 v f r o m p s e a u x v d d v s s a d a p t o r e n d 2 b a t 4 6 w d 3 s s 1 h 1 0 r 3 r 4 3 k 1 k d 4 6 . 8 v d 5 r 5 1 0 0 k r 6 7 . 5 k r 7 1 0 0 k r 8 1 0 0 k q 1 b s s 6 3 l t 1 c 1 0 . 1 f 1 0 0 v d e t r t n v d d c l a s s v s s r 1 2 4 . 9 k r 2 2 8 . 7 t 2 p f t y d 1 s m a j 5 8 a p g d c d c c o n v e r t e r c 2 4 7 f m p 8 0 0 3 a 4 8 v f r o m p s e a u x v d d v s s e n d 2 r 3 1 0 0 k m p 3 9 1 0 m p 3 9 0 8 m p 6 0 0 2 m p 6 0 0 4 m p 6 0 0 1
MP8003A C ieee 802.3 af/at , p o e , powered device , interface controller notice: the information in this document is subject to change without notice. please contact mps for curre nt specifications. users should warrant and guarantee that third party intellectual property rights are not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP8003A rev . 1.0 www.monolithicpower.com 17 7/14/2016 mps proprietary information. patent protected. unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. package information qfn - 1 0 ( 3 mm x 3 mm ) s i d e v i e w t o p v i e w 1 1 0 6 5 b o t t o m v i e w 2 . 9 0 3 . 1 0 1 . 4 5 1 . 7 5 2 . 9 0 3 . 1 0 2 . 2 5 2 . 5 5 0 . 5 0 b s c 0 . 1 8 0 . 3 0 0 . 8 0 1 . 0 0 0 . 0 0 0 . 0 5 0 . 2 0 r e f p i n 1 i d m a r k i n g 1 . 7 0 0 . 5 0 0 . 2 5 r e c o m m e n d e d l a n d p a t t e r n 2 . 9 0 n o t e : 1 ) a l l d i m e n s i o n s a r e i n m i l l i m e t e r s . 2 ) e x p o s e d p a d d l e s i z e d o e s n o t i n c l u d e m o l d f l a s h . 3 ) l e a d c o p l a n a r i t y s h a l l b e 0 . 1 0 m i l l i m e t e r m a x . 4 ) d r a w i n g c o n f o r m s t o j e d e c m o - 2 2 9 , v a r i a t i o n v e e d - 5 . 5 ) d r a w i n g i s n o t t o s c a l e . p i n 1 i d s e e d e t a i l a 2 . 5 0 0 . 7 0 p i n 1 i d o p t i o n b r 0 . 2 0 t y p . p i n 1 i d o p t i o n a r 0 . 2 0 t y p . d e t a i l a 0 . 3 0 0 . 5 0 p i n 1 i d i n d e x a r e a

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